1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, particularly to a method of forming a contact hole aligned with a doped area by means of self-assembly process of diblock copolymer.
2. Description of the Related Art
With the development of semiconductor processing techniques, the critical dimension for a semiconductor device has shrunk increasingly. Issues such as how to form a contact hole with smaller size and how to precisely align a contact hole with an active area have been concerned.
In conventional semiconductor device fabrication, a contact hole landing on an active area is formed by performing photolithography and etching by use of photoresist. Specifically, after forming a gate and doped areas of a semiconductor device on a semiconductor substrate, an interlayer dielectric layer is deposited thereon. The interlayer dielectric layer is planarized by chemical mechanical polishing or other processes. A photoresist is spin-coated on the planarized interlayer dielectric layer and then patterned by photolithography including exposure and development operations and the like. Then, the interlayer dielectric layer is etched by using the patterned photoresist as a mask, until the doped areas are exposed, so as to form the contact holes for those doped areas.
However, with the continuous shrink of the critical dimension of semiconductor devices, the above conventional photolithography has reached its limitation on misalignment control. Misalignment control is especially critical for a contact hole landing on an active area. Position offset between a contact hole formed by the above method and an active area usually occurs, therefore, it is difficult to achieve precise alignment.
FIGS. 1A˜1C are exemplary top views respectively showing different kinds of relative position relationships between a contact hole and a doped area. FIG. 1D is an exemplary sectional view of the semiconductor devices corresponding to FIG. 1A.
FIG. 1A shows the relative position between a contact hole 103 and a doped area 104 in a desired alignment situation, in which the contact hole is located at the centre of the doped area. Referring to its corresponding sectional view, FIG. 1D, reference number 101 represents a recess of an interlayer dielectric layer between two gate lines 105, and reference number 102 represents peaks of the interlayer dielectric layer above those two gate lines 105.
FIG. 1B shows a situation in which the contact hole 103 is shifted with respect to the doped area 104 along a direction parallel to the gate lines 105. In this situation, although there is a shift between the contact hole 103 and the doped area 104, such shift is acceptable because the contact hole 103 still partially contacts the doped area 104 and does not contact any other members.
FIG. 1C shows a situation in which the contact hole 103 is shifted with respect to the doped area 104 along a direction vertical to the gate lines 105. As shown in FIG. 1C, such shift of contact hole 103 may cause to remove a portion of the interlayer dielectric layer above the gate line 105, so as to expose the gate line 105. That is to say, the contact hole 103 would land on both of the gate line 105 and the doped area 104, resulting in the gate line 105 being connected with the doped area 104. Thus, such shift is absolutely unacceptable. Thus, it is desired to avoid the occurrence of such misalignment.
In view of the above problem, it is desired to provide a method of fabricating semiconductor devices which can prevent the occurrence of the above-described misalignment between a contact hole and a doped area, thereby improving the yield of semiconductor devices.